1. Field of the Invention
The present invention relates to an active-matrix substrate used for Liquid-Crystal Display (LCD) devices, and a method of fabricating the same. More particularly, the invention relates to an active-matrix substrate comprising a dielectric plate and switching elements such as Thin-Film Transistors (TFTs) arranged in a matrix array on the plate, and a method of fabricating the substrate.
2. Description of the Related Art
In recent years, active-matrix addressing LCD devices using TFTs as their switching elements have been developed and used practically. LCD devices of this type comprise typically an active-matrix substrate on which gate lines, drain lines and TFTs are regularly arranged; an opposite substrate on which a color filter and a black matrix are formed; and a layer of liquid crystal sandwiched by the active-matrix substrate and the opposite substrate. On operation, a proper voltage is applied across the electrodes formed on the active-matrix substrate and the corresponding electrode or electrodes formed on the opposite substrate, or across the relating electrodes formed on the active-matrix substrate. Thus, the molecules of the liquid crystal are rotated to the specific orientations at the respective pixels according to the applied voltage to thereby change the transmission/reflection characteristic of light at the pixels, thereby displaying desired images on the screen of the LCD device.
With active-matrix addressing LCD devices, it is important to strictly control the orientation of the molecules of the liquid crystal to generate desired high-resolution and high-quality images. To realize this, it is required to enhance the accuracy of substrate flatness, electrode shape, electrode intervals, and so on.
FIG. 1 shows the structure of a prior-art active-matrix substrate of the LCD device of this type, which is fabricated in the following way. Although the substrate actually comprises TFTs, gate lines, and data lines, only one of the TFTs is shown in FIG. 1 for the sake of simplification.
First, a semiconductor layer, which is typically made of amorphous silicon or polycrystalline silicon, is formed on a transparent glass plate 101 and then, it is patterned by using popular photolithography and dry-etching techniques, forming semiconductor islands 112 on the plate 101.
Next, a silicon dioxide (SiO2) layer 117a is formed on the whole surface of the plate 101 to cover the semiconductor islands 112 and patterned, thereby forming gate dielectric layers 117a on the islands 112 for the respective TFTs 102. The remaining layer 117 covers the surface of the plate 101.
A conductive layer is formed to cover the SiO2 layer 117 and the gate dielectric layers 117a over the whole plate 101 and patterned, thereby forming gate electrodes 107a and gate lines (not shown in FIG. 1). The gate lines are connected to the respective electrodes 107a. In other words, specific parts of each gate line serve as the gate electrodes 107a. 
Proper dopant atoms are selectively introduced into the semiconductor islands 112 in self-alignment with respect to the corresponding gate electrodes 107a by the ion-implantation method, thereby forming a source region and a drain region in each of the islands 112. The remaining part of each island 112 between the source and drain regions, which is located below the gate electrode 107a, forms a channel region.
A silicon nitride (SiNx) layer 118 is formed on the SiO2 layer 117a to cover the gate electrodes 107a and the gate lines over the whole plate 101. The layer 118 serves as an interlayer dielectric layer. Then, the layer 118 is selectively removed by the etching method in the peripheral area of each of the islands 112, thereby forming two contact holes that expose the source and drain region 5 of each island 112 by way of the SiO2 and SiNx layers 117 and 118, respectively.
A conductive layer is formed on the interlayer dielectric layer 118 of SiNx over the whole plate 101 and patterned, thereby forming a source electrodes 108a and a drain electrode 108b for each of the TFTs 102, and data lines (not shown in FIG. 1) over the plate 101. The data lines are connected to the corresponding source electrodes 108a of the TFTs 102. Each of the source electrodes 108a is contacted with the source region of the semiconductor island 112 by way of its contact hole. Each of the drain electrodes 108b is contacted with the drain region of the island 112 by way of its contact hole.
Through the above-described process steps, the TFTs 102, the gate lines, and the data lines are formed on the plate 101.
Subsequently, a thick, transparent, dielectric planarization layer 106 is formed on the interlayer dielectric layer 118 to cover the TFTs 102 and the gate and data lines. Contact holes 116 are formed to penetrate the layer 106 at the locations just above the respective source electrodes 108a. These contact holes 116 are to expose the underlying source electrodes 108a from the layer 106.
A transparent conductive layer such as Indium Tin Oxide (ITO) is formed on the planarization layer 106 and patterned, thereby forming pixel electrodes 109 in the respective pixel regions on the layer 106. Each of the pixel electrodes 109 is contacted with a corresponding one of the source electrodes 108a of the TFT 102 by way of its contact hole 116 of the planarization layer 106.
Thus, the prior-art TFT substrate of FIG. 1 is fabricated.
On the other hand, a color filter for red (R), green (G) and blue (B) colors and a black matrix for blocking unnecessary light among the pixels are formed on a transparent glass plate. Thus, an opposing substrate is formed.
Following this, the active-matrix substrate and the opposing substrate are fixed together to keep a specific gap between them with spacers. A specific liquid crystal is filled into the gap and sealed. Thus, the active-matrix LCD device is fabricated.
With the above-described prior-art active-matrix substrate of FIG. 1, the planarization layer 106 is formed to reduce the height difference between the areas including the TFT 102 and the gate and data lines and the other area. However, there is a problem that the height difference is not sufficiently reduced as desired with the use of the layer 106.
In particular, each pixel electrode 109 is raised at its end part 109a near the corresponding TFT 102 with respect to the surface of the plate 101 corresponding to the surface inclination of the layer 106, as shown in FIG. 1. Therefore, the gap between the active-matrix substrate of FIG. 1 and the opposing substrate varies and therefore, the voltage applied across these two substrates becomes non-uniform. This results in a problem of degradation of image quality. This problem is caused by the fact that the TFTs 102 (and the gate and data lines) generate protrusions of the planarization layer 106 and at the same time, each of these protrusions is considerably wide.
To solve the above-described problem, the inventor created the following improvement and submitted it as a Japanese patent application.
Specifically, prior to the formation of the TFTs, a transparent dielectric layer is selectively formed on a transparent plate except for the areas for the TFTs and the gate and data lines. The transparent dielectric layer has a thickness equal to or greater than the height difference between the areas including the TFTs and the gate and data lines and the other area. With this technique, the area for each pixel electrode is planarized by the transparent dielectric layer and therefore, the above-identified problem can be solved.
The structure of the active-matrix substrate and a method of fabricating the same according to the above-described inventor's improvement are explained below with reference to FIGS. 2A to 2C. FIG. 2C is a plan view showing the arrangement of the pixels including the TFTs, the gate and data lines, and the pixel electrodes. FIGS. 2A and 2B are cross-sectional view along the line IIB—IIB in FIG. 2C before and after the TFTs are formed, respectively.
First, transparent dielectric layer 113 is formed on a glass plate 101. The layer 113 has a thickness greater than the height difference H of the TFTs 102 from the surface of the plate 101. Then, the layer 113 is selectively removed by using known photolithography and etching techniques in such a way as to be left on the areas that exclude the TFTs 102 and the gate and data lines. In these areas, the pixel electrodes 109 are formed in the later process steps. The layer 113 is made of, for example, SiO2. The removed parts of the layer 113 form recesses 105a and 105b on the plate 101. The recesses 105a, each of which has an approximately rectangular cross-section, are formed to extend in a horizontal direction in FIG. 2C along the respective gate lines 107. The recesses 105b, each of which has an approximately rectangular cross-section, are formed to extend in a vertical direction in FIG. 2C along the respective data lines 108. The recesses 105a and 105b form rectangular pixel regions, as clearly shown in FIG. 2C.
Thereafter, the TFTs 2 having the same structure as shown in FIG. 1 are formed near the respective intersections of the recesses 105a and 105b. The pixel electrodes 109 are formed on the remaining transparent dielectric layer 113 in the respective pixel regions. The pixel electrodes 109 are connected to the source electrodes 108a of the corresponding TFTs 102 by way of the relating connection parts 110 of the electrodes 109. The connection parts 110 are extended over the height-different portions between the TFTs 102 and the pixel regions. The TFTs 102, the gate lines 107, and the data lines 108 are all located in the recesses 105a and/or 105b. 
As shown in FIG. 2C, the gate lines 107 are extended horizontally in the respective horizontal recesses 105a while the data lines 108 are extended vertically in the respective vertical recesses 105b. The TFTs 102 are located near the respective intersections of the gate and data lines 107 and 108 (or, the recesses 105a and 105b).
With the active-matrix substrate according to the inventor's improvement shown in FIGS. 2A to 2C, the recesses 105a and 105b are small in width and occupy narrow areas compared with the size of the plate 101. On the other hand, the surface of the remaining transparent dielectric layer 113 is flat and occupies a wide area of the plate 101. As a result, it may be said that almost all the surface of the active-matrix substrate is flat, which leads to the solution of the above-described problem.
With the method of fabricating the active-matrix substrate according to the inventor's improvement shown in FIGS. 2A to 2C, however, there is a disadvantage that the patterning accuracy for the formation of the TFTs 102 is difficult to be controlled, and that the transparency at the pixel regions deteriorates to darken the displayed images.
Specifically, in this method, the transparent dielectric layer 113 is formed and patterned to form the recesses 105a and 105b and thereafter, the TFTs 102 and the gate and data lines 107 and 108 are formed in the recesses 105a and 105b. Thus, because of the effect of the height difference H between the layer 113 and the bottoms of the recesses 105a and 105b, each photoresist film used therefor has unavoidably a large thickness. As a result, there is a problem that desired fine patterns for the TFTs 102 are difficult to be formed in the respective photoresist films.
Moreover, because of the same reason, dry etching processes need to be carried out for forming the holes or recesses with large aspect ratios and thus, the dimensional accuracy is difficult to be controlled in the dry etching processes. Concretely, for example, when a photoresist film to be used for forming holes or recesses with a depth of approximately 1 μm has a thickness of approximately 2 μm, a possible focal point difference will be approximately 1 μm in the exposure process for the photoresist film. As a result, the dimensional accuracy of the patterned photoresist film will deteriorate.
In addition, as shown in FIG. 3, as the fabrication process steps are carried out, a plurality of interlayer dielectric layers 114 are successively formed on the patterned transparent dielectric layer 113. These dielectric layers 114 are stacked not only on the layer 113 but also along the sidewalls. In particular, the effective thickness of the stacked layers 114 along the sidewalls with respect to the exposing light irradiated will be increased in the regions 120. Therefore, undesired reflection and/or refraction of the exposing light tend to occur in the regions 120, in other words, the regions 120 tends to be transmittance-decreased regions, resulting in quality degradation of displayed images.